Biasing the MOSFET

BIASING THE MOSFET

Biasing of Enhancement MOSFET

Fig. 2.11 shows the drain-to-gate bias circuit for enhancement mode MOSFET.

Here the gate bias voltage is This circuit offers the dc stabilization through the feedback resistor R_f. However, the input resistance is reduced because of Miller effect.

Also the voltage divider biasing technique given for JFET can be used for the enhancement MOSFET. Here, the dc stability is accomplished by the de feedback through R_S.

But the self bias technique given for JFET cannot be used for establishing an operating point for the enhancement MOSFET because of the voltage drop across R_S is in a direction to reverse bias the gate and it actually needs forward gate bias.

Fig. 2.12 shows an N- channel enhancement mode MOSFET common source circuit with source resistor. The gate voltage is

and the gate to source voltage is

V_GS = V_DD - V_G

Assuming that V_GS > V_TN and the MOSFET is biased in the saturation region, the drain current is

Here the threshold voltage V_TN and conduction parameter K_N are functions of temperature.

The drain to source voltage is

V_DS = V_DD – I_D R_D

If V_DS > V_{DS (sat)} = V_GS – V_TN, then the MOSFET is biased in the saturation region. If V_DS < V_{DS (sat)} = V_GS – V_TN, then the MOSFET is biased in the non saturation region, and the drain current is given by

Biasing Depletion MOSFET

Both the self-bias technique and voltage divider bias circuit given for JFET can be used to establish an operating point for the depletion mode MOSFET.